🧠 Central Processing Unit (CPU)

Brain of computer. Contains Control Unit (CU) and Arithmetic Logic Unit (ALU). No other component determines overall performance as much as CPU. When entire CPU on a single silicon chip → microprocessor.

📏 Word Size & Registers

Word size = length of registers (bits). 32/64/128-bit common. Larger word size → faster processing. Registers are high-speed temporary storage inside CPU (not main memory). Key registers:

• MAR – holds address of active memory location.
• MBR – holds data on way to/from memory.
• PC (Program Counter) – holds address of next instruction.
• Accumulator (A) – holds data/result of operations.
• IR (Instruction Register) – holds current instruction being executed.
• I/O Register – communicates with I/O devices.

🕹️ Instruction Set & Backward Compatibility

Instruction set = built-in machine instructions (add, compare, etc.). Different CPUs have different sets. Manufacturers group CPUs into families with backward compatibility (new CPU includes all instructions of predecessor). Allows software upgrades without rewriting.

⏱️ Processor Speed & Clock

System clock emits pulses (cycles). Speed measured in MHz/GHz. 1 GHz = 10⁹ cycles/sec. Superscalar CPUs execute >1 instruction per cycle (multiple ALUs). Speed units: PC → MHz/GHz; workstations/mainframes → MIPS/BIPS; supercomputers → MFLOPS, GFLOPS, TFLOPS, PFLOPS.

🏛️ CISC vs RISC vs EPIC

• CISC (Complex Instruction Set): large instruction set, variable-length instructions, complex hardware (e.g., x86).
• RISC (Reduced Instruction Set): small fixed-length instructions, fewer addressing modes, faster & cheaper (SPARC, POWER, PA-RISC).
• EPIC (Explicitly Parallel Instruction Computing): compiler-driven parallelism, predication, speculation. Intel Itanium (IA-64) example.

🧩 Multicore & Power-Efficient Processors

Multiple cores on one chip (dual-core, quad-core, up to 64 cores). Better parallel performance, less heat/power than single-core. Power-efficient tech: Demand Based Switching (DBS) – adjusts frequency & voltage based on workload. Reduces total cost of ownership (TCO).

🗄️ Main Memory Organization

Memory = array of addressable locations (words). Each word has unique address. Word length = bits per location. Memory operations: read (non-destructive), write (destructive). Word-addressable (fixed length) vs character-addressable (variable length). Capacity: KB (2¹⁰), MB (2²⁰), GB (2³⁰), TB, PB.

💾 RAM & ROM Types

• RAM (volatile): Dynamic RAM (DRAM) – needs refresh; Static RAM (SRAM) – faster, costlier, used for cache.
• ROM (non-volatile): fixed data, burned in. PROM (user programmable once), EPROM (erasable – UV or EEPROM/Flash).
• Cache memory: extremely fast buffer between CPU and main memory, stores active data/instructions to reduce speed mismatch.

📊 Memory Characteristics Table